Cadence and Samsung Foundry Expand 2nm and 3D-IC Partnership to Power the Next Wave of AI Computing
Cadence and Samsung Foundry have announced a significant expansion of their strategic collaboration, strengthening support for next-generation AI infrastructure, high-performance computing (HPC), and emerging physical AI applications through advanced 2nm semiconductor technology and 3D integrated circuit (3D-IC) design solutions.
The multi-year agreement extends the development of Memory and Interface IP portfolios while enhancing certification of Cadence’s AI-driven electronic design automation (EDA) and system design and analysis (SDA) tools on Samsung Foundry’s second-generation 2nm manufacturing process. The collaboration aims to provide semiconductor companies with a production-ready platform capable of addressing the increasing complexity of AI-focused chip designs.
Meeting the Growing Demands of AI Infrastructure
As artificial intelligence continues to evolve, demand for more powerful and efficient computing platforms is accelerating across data centers, edge computing devices, robotics, autonomous systems, and physical AI applications.
Building upon their previous collaboration announced in 2025, Cadence and Samsung Foundry are broadening support for advanced semiconductor designs through an expanded portfolio of Memory and Interface IP solutions. These include NVIDIA NVLink-C2C-enabled connectivity technologies and CUDA-X GPU-accelerated libraries covering:
- High-speed SerDes interfaces
- PCIe connectivity
- UCIe chiplet interconnects
- Next-generation memory interfaces
These technologies are optimized for Samsung Foundry’s second-generation 2nm process node, helping customers achieve improved performance, reduced power consumption, and faster development cycles.
According to Boyd Phelps, Senior Vice President and General Manager of Cadence’s Silicon Solutions Group, AI infrastructure and physical AI applications are driving unprecedented requirements for advanced process nodes and 3D-IC architectures, making robust design platforms increasingly critical.
AI-Optimized Design Flows for Advanced Semiconductor Development
The collaboration also focuses heavily on enabling AI-enhanced semiconductor design workflows.
Cadence’s certified design platform on Samsung’s second-generation 2nm process includes several key tools:
- Innovus Implementation System for digital design implementation
- Virtuoso Studio for custom and analog chip design
- Integrity 3D-IC Platform for complete 3D chip planning and implementation
- Voltus IC Power Integrity Solution for power analysis
- Quantus Extraction Solution
- Tempus Timing Solution for final signoff verification
The platform introduces advanced features such as glitch power optimization and intelligent hierarchical design flows, helping engineers achieve better performance, power efficiency, and area utilization while reducing turnaround times.
Advancing 3D-IC and Hybrid Bonding Technologies
A major focus of the partnership is support for Samsung’s 3D Cube-H technology, which utilizes Hybrid Copper Bonding (HCB) to enable more advanced multi-die packaging architectures.
Cadence’s design ecosystem supports:
- Full system-level planning
- 3D implementation workflows
- Silicon interposer auto-routing
- Automated optimization
- Signoff verification
Tools such as Cerebrus Intelligent Chip Explorer, Integrity 3D-IC, Innovus, Voltus, Tempus, and Pegasus Verification System work together to streamline the development of complex 3D semiconductor packages.
The result is tighter integration between design, verification, and signoff processes, enabling higher confidence in advanced AI and HPC chip deployments.
NVIDIA Supports Next-Generation AI Interconnect Development
The expanded collaboration also benefits NVIDIA, which is utilizing the combined capabilities of Cadence and Samsung Foundry to develop future AI computing platforms.
Central to these efforts is NVIDIA’s NVLink-C2C technology, which provides high-bandwidth chip-to-chip connectivity critical for modern accelerated computing systems.
Timothy Costa, Vice President and General Manager of Computational Engineering at NVIDIA, noted that AI workloads continue to increase in complexity, requiring more advanced simulation and design capabilities. By leveraging Cadence’s GPU-accelerated design tools alongside Samsung Foundry’s second-generation 2nm technology, NVIDIA aims to optimize the development of future AI architectures and high-speed interconnect technologies.
Ambarella Developing Next-Generation 2nm Edge AI Platform
The collaboration is also supporting edge AI specialist Ambarella in developing its upcoming 2nm AI platform.
Ambarella’s next-generation solution is designed for intelligent edge applications, including:
- Robotics
- Autonomous machines
- Drones
- Advanced vision systems
- Physical AI deployments
The company is leveraging Cadence and Samsung Foundry technologies to implement PCIe 5.0 connectivity while managing the growing complexity of advanced-node chip design and manufacturing.
Ambarella believes the availability of production-ready IP, validated design tools, and mature process design kits (PDKs) significantly reduces development risk while accelerating innovation in low-power AI perception and edge computing solutions.
Driving the Future of AI Silicon
As AI adoption expands across industries, semiconductor companies face increasing pressure to deliver higher performance, greater efficiency, and more advanced integration technologies.
The enhanced partnership between Cadence and Samsung Foundry addresses these challenges by combining cutting-edge 2nm manufacturing, advanced IP solutions, AI-driven design automation, and comprehensive 3D-IC development capabilities.
Both companies are expected to showcase the latest developments from their collaboration during the Samsung Advanced Foundry Ecosystem (SAFE) 2026 event, where attendees will have the opportunity to explore demonstrations and technical sessions focused on second-generation 2nm design flows and GPU-accelerated AI workloads.
