September 25, 2026

Cadence PCIe 6.0 Subsystem Achieves First-Pass Compliance on TSMC N3

Cadence Design IP

Cadence has announced that its PCI Express (PCIe) 6.0 PHY and controller IP, implemented on TSMC’s N3 process, has successfully passed its first official PCI-SIG compliance testing.

The complete x8 PCIe 6.0 subsystem was tested at the standard’s full 64 GT/s data rate during the PCI-SIG compliance workshop held in late July. Cadence said the solution passed all official compliance tests and has been added to the PCI-SIG Integrators List, marking an important step towards production deployment.

The subsystem combines Cadence’s PCIe 6.0 PHY and controller IP in a complete silicon implementation. The company said the successful first-pass result demonstrates interoperability and provides customers with a validated solution for integrating PCIe 6.0 connectivity into next-generation systems.

Cadence worked with PCI-SIG, test equipment manufacturers and industry partners ahead of the compliance workshop to conduct interoperability testing and address potential issues before formal certification.

PCIe 6.0 is designed to meet the growing bandwidth requirements of AI and high-performance computing (HPC) infrastructure. The technology can be used for accelerator cards, network interfaces and storage devices, with applications expected to expand across data centres, AI infrastructure, automotive and enterprise systems as the ecosystem develops.

Cadence’s PCIe 6.0 solution includes ADC- and DSP-based equalisation, firmware-optimised SerDes operation, multi-protocol support and low-power optimisation. The x8 implementation is certified on the TSMC N3 process and supports the latest PCI-SIG engineering change notices.

AI accelerator company Positron AI has also licensed Cadence’s PCIe 6.0 SerDes IP for its AI inference accelerator chip, citing the subsystem’s silicon implementation and interoperability testing as important factors for high-bandwidth connectivity.

Cadence said its complete PCIe 6.0 subsystem, including PHY and controller, is available now for SoC developers. The company also offers PCIe solutions supporting specifications up to PCIe 7.0.