Cadence Introduces Maestro AI Model Portfolio for Smarter Chip and System Design

Cadence (Nasdaq: CDNS) has announced its Maestro AI Model Portfolio, a collection of domain-specialized AI models designed to power its Cadence AI Super Agents across semiconductor and system design workflows.

By combining specialised AI models with reinforcement learning (RL), electronic design automation (EDA) and system design automation (SDA) tools, Cadence aims to create an integrated engineering platform that improves design results, accelerates development and continuously learns from verified outcomes.

The Maestro portfolio includes domain-specialized large language models (LLMs), trained decision models and self-improving agent skills. It works alongside Cadence AI Super Agents such as AuraStack, ChipStack, InnoStack and ViraStack to handle complex engineering tasks.

The platform combines frontier, open-weight and domain-specialized models, with deployment options across cloud and on-premises environments.

Continuous Learning Through Reinforcement Learning

One of Maestro’s key features is its ability to learn from engineering results through reinforcement learning.

Cadence reports initial results showing up to 30% improvement in quality of results and up to 5X greater token efficiency compared with a general-purpose foundation model.

These improvements come from combining Cadence’s engineering knowledge, curated datasets, AI Super Agents and automation tools. Outputs are evaluated against engineering objectives, design constraints and verified results, creating feedback loops that allow the AI models to improve their decisions over time.

Combining AI Capabilities with Engineering Expertise

Maestro is designed to work alongside different AI models rather than relying on a single model for every task.

Frontier and open-weight models provide general reasoning and language capabilities, while Maestro delivers specialised knowledge for chip and system engineering.

Cadence AI Super Agents can interpret design requirements, break them into tasks, generate design content, analyse results and evaluate engineering trade-offs. The models can also be further trained using customers’ proprietary data, designs and workflows.

By balancing AI model usage with direct EDA and SDA tool operations, Cadence aims to reduce token consumption while maintaining efficiency.

The complete platform can run through Cadence’s secure cloud, supported public cloud environments or customer-controlled on-premises infrastructure to meet different security and data privacy requirements.

Collaboration with NVIDIA and Industry Partners

Cadence is working with NVIDIA to strengthen Maestro’s AI and engineering capabilities. The collaboration brings together NVIDIA Nemotron, OpenShell and engineering expertise, using feedback from EDA tools and deterministic solvers to help AI agents make better design decisions.

Cadence is also integrating agent security capabilities through the NVIDIA OpenShell Reference Architecture.

Industry partners have highlighted the potential benefits. Socionext COO Hisato Yoshida said the company is deploying Cadence’s InnoStack AI Super Agent in its production design environment, with expectations of up to 5X overall productivity gains while maintaining design quality.

Silicon Labs has also reported improvements in root-cause analysis and debugging during pre-silicon low-power verification using Cadence Verisium Debug as part of the ChipStack AI Super Agent.

Availability

The first Maestro AI models are expected to become available to selected early-access customers in Q4 2026.

With Maestro, Cadence aims to bring specialised AI intelligence into semiconductor and system engineering, helping teams improve productivity and accelerate complex design workflows.